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GE 750-P5-G5-S5-HI-A1-R-E Feeder Management Relay
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- Part Number: 750-P5-G5-S5-HI-A1-R-E
- Brand: GE Fanuc
- Type: Feeder Management Relay
- Dimensions: 2.1x18.6x26.3cm
- Country of Origin: USA
- Barcode: 8537101190
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Additional Specifications
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Product Description
Configured for high-speed current monitoring and programmable line protection in substation distribution grids, the GE Multilin 750-P5-G5-S5-HI-A1-R-E (750 Feeder Management Relay) provides direct physical/electrical execution. The hardware platform samples secondary phase, ground, and sensitive zero-sequence currents to perform algorithmic fault evaluation and circuit breaker trip routing.
Hardware Specifications
| Parameter | Specification |
|---|---|
| Model | 750-P5-G5-S5-HI-A1-R-E |
| Brand | GE Multilin (General Electric) |
| Origin | United States / Canada |
| Weight | 14.00 lbs |
| Dimensions | Standard SR750 horizontal drawout chassis profile |
| Operating Temp | Standard substation panel environment limits |
| Power Consumption | Sourced via internal multi-range power supply module |
| Control Power Input | 80–300 V DC or 70–265 V AC continuous |
| Line Frequency Tolerance | 48/62 Hz frequency limits |
| Phase Current Inputs | Three-channel 5 A phase current transformer loops |
| Ground Current Input | One-channel 5 A zero-sequence current transformer link |
| Sensitive Ground Input | One-channel 5 A sensitive current monitoring pathway |
| Analog Output Config | Eight channels of isolated 4-20 mA current loops |
| Local Display Indicators | Red breaker closed LED, enhanced (ENH) front panel assembly |
| Product Category | Overcurrent Relays / Controls & Indicators |
Backplane Bus Communication Velocity and Firmware Architecture
The feeder protection assembly utilizes high-density internal bus traces to maintain deterministic microsecond communication cycles across all sensing and execution sub-modules. Hardware timing circuits dictate that physical current signals are processed through active analog-to-digital converters, matching the firmware flash compatibility criteria of the core SR750 CPU matrix. This configuration maintains immediate logic resolution under maximum line fault spikes, ensuring that the internally calculated overcurrent tripping sequences broadcast to output contacts without encountering bus bottlenecks.
Frequently Asked Questions
Q: How does the hardware architecture isolate the multiple current monitoring paths on the 750-P5-G5-S5-HI-A1-R-E?
A: The relay provides separate internal isolation transformers for the 5 A phase current inputs, the 5 A zero-sequence ground input, and the dedicated 5 A sensitive ground pathway. This separation ensures that low-level earth leakage measurements are not corrupted by high-magnitude phase current transients over the internal bus structure.
Q: What are the interface assignment constraints for the eight integrated 4-20 mA analog outputs?
A: The eight analog loops run on an integrated internal current source configuration that provides a fixed 4-20 mA output span. These loops are individually mapped within the engineering firmware to mirror specific digitized line metrics, including active phase current magnitudes, calculated thermal load percentages, or frequency drift.
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